MARTe2 run test
- output port mapped correctly
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- algos/SCDalgo_template/SCDalgo_template.slx 0 additions, 0 deletionsalgos/SCDalgo_template/SCDalgo_template.slx
- algos/SCDalgo_template/SCDalgo_template_loadtp.m 1 addition, 1 deletionalgos/SCDalgo_template/SCDalgo_template_loadtp.m
- algos/SCDalgo_template/SCDalgo_template_signal_buses.m 13 additions, 7 deletionsalgos/SCDalgo_template/SCDalgo_template_signal_buses.m
- code/classes/SCDsignal/ProductionState.m 1 addition, 1 deletioncode/classes/SCDsignal/ProductionState.m
- code/classes/SCDsignal/QualityTag.m 1 addition, 1 deletioncode/classes/SCDsignal/QualityTag.m
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