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SPC
SCDDS
SCDDS-core
Commits
6170e346
Commit
6170e346
authored
3 years ago
by
Federico Felici
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Update template algo to avoid separate harness.slx
parent
f1780a06
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algos/SCDalgo_template/SCDalgo_template.slx
+0
-0
0 additions, 0 deletions
algos/SCDalgo_template/SCDalgo_template.slx
algos/SCDalgo_template/SCDalgo_template_harness_run.m
+36
-15
36 additions, 15 deletions
algos/SCDalgo_template/SCDalgo_template_harness_run.m
with
36 additions
and
15 deletions
algos/SCDalgo_template/SCDalgo_template.slx
+585 B (+3%)
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6170e346
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algos/SCDalgo_template/SCDalgo_template_harness_run.m
+
36
−
15
View file @
6170e346
function
SCDalgo_template_harness_run
(
obj
)
% run harness and check the result
% load tunable control parameters from mds
shot
=
100
;
% shot reference
obj
.
actualizeparameters
(
shot
);
% set input
input_name
=
'input_harness'
;
input
.
amplitude
=
single
(
1
);
input
.
period
=
0.1
;
assignin
(
'base'
,
input_name
,
input
)
% Input Data - must be structure of timeseries matching input bus structure
time
=
0
:
obj
.
gettiming
.
dt
:
1
;
data
=
single
(
sin
(
2
*
pi
*
time
*
10
)
'
);
tsStructData
=
struct
(
'signal'
,
timeseries
(
data
,
time
,
'Name'
,
'Test Input Data'
));
% load tunable control params from mds
obj
.
actualizeparameters
(
shot
);
% SimIn object to customize configuration of Simulation run for test
SimIn
=
Simulink
.
SimulationInput
(
obj
.
getname
);
% Create template Input dataset for this model
Dataset
=
createInputDataset
(
obj
.
getname
);
% run sim
result
=
sim
(
'SCDalgo_template_harness.slx'
,
'ReturnWorkspaceOutputs'
,
'on'
);
% assign input data signal to Simulink.Signal object
DataIn
=
Simulink
.
SimulationData
.
Signal
;
DataIn
.
Values
=
tsStructData
;
% check result
% assign as first element in input data set
isig
=
find
(
contains
(
Dataset
.
getElementNames
,
'signal_in'
));
% find input signal index
Dataset
=
Dataset
.
setElement
(
isig
,
DataIn
);
%#ok<FNDSB>
SimIn
.
ExternalInput
=
Dataset
;
% assign this as external input for simulation
% Custom parameters for this run to save outport data
SimIn
=
SimIn
.
setModelParameter
(
'SaveOutput'
,
'on'
);
% set to save outport signals
SimIn
=
SimIn
.
setModelParameter
(
'SignalLogging'
,
'on'
);
% set to save log signals
SimIn
=
SimIn
.
setModelParameter
(
'OutputSaveName'
,
'SimOut'
);
SimIn
=
SimIn
.
setModelParameter
(
'SaveFormat'
,
'Dataset'
);
SimIn
=
SimIn
.
setModelParameter
(
'StartTime'
,
num2str
(
time
(
1
)));
SimIn
=
SimIn
.
setModelParameter
(
'StopTime'
,
num2str
(
time
(
end
)));
SimIn
=
SimIn
.
setModelParameter
(
'FixedStep'
,
num2str
(
mean
(
diff
(
time
))));
% simulate - simulate only single types to save time
result
=
sim
(
SimIn
);
% check output port data
tp
=
SCDalgo_template_loadtp
;
output
=
result
.
s
im
o
ut
.
signal
;
output
=
result
.
S
im
O
ut
{
1
}
.
Values
.
signal
;
assert
(
max
(
output
.
Data
)
==
tp
.
gain
,
'Wrong output!'
);
% check logs
logsout
=
result
.
logsout
;
signal
=
logsout
.
getElement
(
'signal'
)
.
Values
;
assert
(
max
(
signal
.
Data
)
==
input
.
amplitude
,
'Wrong input!'
);
evalin
(
'base'
,
sprintf
(
'clear(
''
%s
''
)'
,
input_name
)
);
% clear input in workspace
signal
=
logsout
.
getElement
(
'signal_in'
)
.
Values
.
signal
;
assert
(
all
(
signal
.
Data
==
tsStructData
.
signal
.
Data
),
'Logged signal does not match input!'
);
end
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