Commit 10dea8b5 authored by Pierre Guillod's avatar Pierre Guillod 😸
Browse files

remove obsolete comments

parent 56482e9a
// ============================================================================
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.1 :| Alexandra Du :| 06/01/2016:| Added Verilog file
// ============================================================================
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
module DE10_LITE_Golden_Top(
// input ADC_CLK_10,
......
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